1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
In recent years, concerning the DRAM (dynamic random access memory) which is an example of a semiconductor device, pads for electrically connecting an internal circuit to the outer part of a chip, and that are arranged in a center part of the chip, have been attracting attention. An example of such DRAMs is disclosed in JP2009-038142A.
A plurality of pads, such as a data input/output (DQ) pad, an address pad, a control pad, a power supply voltage (VDD) pad and a ground potential (VSS) pad, are usually provided respectively according to the purpose of each of the plurality of pads. Hereinafter, a configuration in which a plurality of pads are arranged in a row in a certain direction is called as “pad row”.
The semiconductor chip disclosed in JP2009-038142A is an example in which one pad row is adopted. In such chips as described above, research has conducted into cases in which two parallel pad rows are arranged in the center part of the chip in response to an increase in the number of DQ pads.
On the other hand, to adapt to various products on which a DRAM is to be mounted, DRAMs are provided mainly in three product types, “×8”, “×16” and “×32”, in terms of the number of data inputs/outputs. For this reason, research has been conducted into cases in which pad rows, which can adapt to any of 8 DQ pads (a case where the number of data inputs/outputs is “×8”), 16 DQ pads (a case where the number of data inputs/outputs is “×16”) and 32 DQ pads (a case where the number of data inputs/outputs is “×32”), are used. As an example, there is a method as described below. When a chip in which 32 DQ pads are arranged to be adaptable to DQ pads, whose number of data inputs/outputs is “×32”, which is the number at which the number of DQ pads reaches a maximum, is fabricated and shipped to customers with the number of data inputs/outputs of “×16” or “×8”, the three product types with different numbers of data inputs/outputs are realized with one kind of common chip in such a manner as to ensure that unnecessary DQ pads are not connected to a printed circuit board.
An example of the configuration of the BGA (ball grid array) of a DRAM chip provided with two pad rows will be described with reference to a drawing. It is assumed that the chip to be mounted on this BGA is a common chip adaptable to any of the numbers of data inputs/outputs “×8”, “×16”, and “×32”.
For pads formed on the DRAM chip, there are DQ pads for performing data input/output and CA pads for receiving command signals and address signals, as pads associated with signal input/output. The CA pads are arranged in a center part of the DRAM chip to be adaptable to the three product types with different numbers of data inputs/outputs. Pads for 8 bits, for “×8”, and for the remaining 8 bits used in “×16”, in addition to the 8 bits, are arranged in one section of the CA pads of the chip, and pads for the remaining 16 bits used in “×32” are arranged in another section of the CA pads. In other words, the DQ pads are arranged so as to be sandwiched by the pads for 16 bits used in “×16” and the pads for the remaining 16 bits used in “×32” in the direction of the long side of the chip.
FIG. 1 is a perspective view showing an example of the configuration of a related semiconductor device.
As shown in FIG. 1, chip 302 is provided on package 301. FIG. 1 shows an enlarged portion corresponding up to approximately ⅓ of package 301 from one of the two short sides of package 301 on which rectangular chip 302 is mounted.
On a surface of package 301, there are provided electrode pads for solder balls for electrically connecting package 301 and a printed circuit board on which this package 301 is to be mounted. The positions of the electrode pads for solder balls are specified in standards such as DDR2 (double data rate 2) and DDR3. VDD electrodes 151 and 152 are electrode pads for solder balls for supplying a power supply voltage to chip 302. VSS electrodes 153 and 154 are electrode pads for solder balls for supplying a ground potential to chip 302. Address input electrode 171 is an electrode pad for a solder ball to which signals for specifying each of addresses A0 to A12 and BA0 to BA2 are inputted. FIG. 1 is a perspective view obtained when package 301 is viewed from the surface on the side where solder balls are attached.
Two pad rows are provided in the center part of chip 302 parallel to the long side of chip 302. Pads 111, 112 and 116 (hereinafter referred to as VSSSA pads) are sense amplifier grounding pads which supply a ground potential to sense amplifiers. Pad 113 (hereinafter referred to as a VSSP pad) is a pad for supplying a ground potential to a power-up voltage generating circuit. Pad 114 (hereinafter referred to as a VSSI pad) is a pad for supplying a ground potential to an input first-stage circuit. In particular, an input first-stage circuit is apt to be affected by noise because the input first-stage circuit detects small potential differences.
Pad 122 (hereinafter referred to as a VDDSA pad) is a sense amplifier power supply pad for supplying a power supply voltage to a sense amplifier. Pad 121 (hereinafter referred to as a VDDP pad) is a pad for supplying a power supply voltage to the power-up voltage generating circuit. Pads 123 and 124 (hereinafter referred to as VDDI pads) are pads for supplying a power supply voltage to the input first-stage circuit.
Interconnects are provided from the electrode pads for solder balls near to the pad rows, and the pads of the pad rows and the interconnects are connected by bonding wires 391. VSSSA pads 111 and 112, VSSP pad 113, and VSSI pad 114 are connected to VSS electrode 153 via bonding wires 391 and VSS interconnect 363. VSSI pad 115 and VSSSA pad 116 are connected to VSS electrode 154 via bonding wires 391 and VSS interconnect 364.
VDDP pad 121, VDDSA pad 122, and VDDI pads 123 and 124 are connected to VDD electrodes 151 and 152 via bonding wires 391 and VDD interconnect 361.
Incidentally, in FIG. 1, the case where the number of data inputs/outputs is “×32” is shown for the connection of each of various pads 111 to 116 and 121 to 124 and the VSS interconnects or the VDD interconnects. For other pads, part of the case where the number of data inputs/outputs is “×8” or “×16” is shown.
In package 301 shown in FIG. 1, in a case where there are a plurality of pads connected to the same potential in one of the two pad rows on the left side and the right side, the plurality of pads are connected to the electrodes for solder balls via the interconnects on the side near the pad row. A specific example will be described with reference to FIG. 1. VSSSA pads 111 and 112, VSSP pad 113, and VSSI pad 114 in the pad row on the left side are connected to VSS electrode 153 via VSS interconnect 363. VSSI pad 115 and VSSSA pad 116 in the pad row on the right side are connected to VSS electrode 154 via VSS interconnect 364.
As described above, in the configuration shown in FIG. 1, in a case where a ground potential VSSSA pad and a VSSI pad are provided in the same pad row, each of these pads is commonly connected to a VSS interconnect which is nearest to each pad.
However, noise may sometimes be generated in a VSSSA pad due to variations in the potential within a sense amplifier while the sense amplifier is working. In this case, in the configuration shown in FIG. 1, noise reaches the VSSI pad from the VSSSA pad via the VSS interconnect and is superimposed on the VSSI pad and therefore it becomes necessary to reduce the operating frequency in order to ensure that the input first-stage can receive input data without an error even under the influence of the noise. This causes a worsening of the operating characteristics (concretely, the operating frequency) of the chip.